Edge pad architecture for semiconductor memory

A memory component comprising:

• a plurality of memory bank arrays;
• a data path coupled to each of the plurality of memory bank arrays;
• and
• at least two sets of data pads coupled to the data path and configured with the data path to bus data to and from the memory bank array and configured such that each of the data pads of each of the two sets of data pads are located adjacent the first and second edges of the memory component;
• wherein the memory component is configurable for a plurality of applications such that in a first application only data pads of the first set of data pads are used to bus data and such that in a second application data pads of both the first and second sets of data pads are used to bus data.

A memory component comprising:

• a plurality of memory bank arrays;
• a data path coupled to each of the plurality of memory bank arrays;
• and
• a first set of data pads adjacent a first edge of the memory component and coupled to the data path to bus data to and from the memory bank array;
• a second set of data pads adjacent a second edge of the memory component and coupled to the data path to bus data to and from the memory bank array;
• and
• means for selectively configuring the memory component for a plurality of applications such that in a first application only data pads of the first set of data pads are used to bus data and such that in a second application data pads of both the first and second sets of data pads are used to bus data.

A method for configuring a memory component, the method comprising:

• writing data to and reading data from at least one memory bank array;
• bussing data between a plurality of data pads and the at least one memory bank array, the data pads being located adjacent first and second edges of the wafer;
• and
• alternatively configuring the memory component for one of a first application and a second application, wherein the first application only uses data pads located on the first edge of the wafer to bus data and wherein the second application uses data pads located on both the first edge of the wafer and one the second edge of the wafer to bus data.