US 2007/0164366 A1 · Mitigation of gate oxide thinning in dual gate CMOS process technology

Abstract

Excessive thinning of a thin oxide in a dual gate CMOS fabrication process is mitigated. A thick gate oxide utilized to form high voltage transistors is selectively patterned to leave some thick oxide in an active area where low voltage transistors are formed. Due to fabrication conditions, the thin gate oxide that is formed in an active area where the low voltage transistors are formed may become too thin, particularly in perimeter areas of the low voltage area. Accordingly, the thick gate oxide is patterned so that some of it remains in perimeter areas of the low voltage active area. This mitigates leakage and/or other unwanted conditions that may result if low voltage transistors are formed using the gate oxide that is too thin.

Claims20

Dependent claims

A method of mitigating over thinning of a low voltage gate dielectric in a dual gate CMOS fabrication process, comprising:

forming a first gate dielectric material to a first thickness in high and low voltage active areas on a semiconductor substrate;
selectively removing some of the first gate dielectric material in the low voltage active area so that some of the first gate dielectric material remains in the low voltage area but some of the substrate is exposed in the low voltage active area;
forming a second gate dielectric material to a second thickness in the low voltage active area over the exposed substrate;
and
forming a conductive gate electrode material over at least some of the first gate dielectric material in the high voltage active area and over at least some of the first gate dielectric material and the second gate dielectric material in the low voltage active area.

2 more elements

Dependencies are inferred from the claim text.

Mitigation of gate oxide thinning in dual gate CMOS process technology

Life of this patent

Mitigation of gate oxide thinning in dual gate CMOS process technology

Life of this patent

Abstract

Claims20