SET/RESET latch circuit, Schmitt trigger circuit, and MOBILE based D-type flip flop circuit and frequency divider circuit thereof

A SET/RESET latch circuit, comprising:

• a plurality of transistors, each emitter of said transistors is connected to a common current source,
• a negative differential resistance diode is connected to each collector of said transistors;
• and
• collector terminals of said transistors respectively serving as non-inverted and inverted output terminals;
• wherein the circuit satisfies the relationship:
• IP<IEE2·IP
• where, IP:
• the peak current of said negative differential resistance diode, and
• IEE:
• the current of the current source connected in series to the common node of emitters of said transistors.
• thereby providing differential Non-Return-to-Zero mode outputs when Return-to-Zero mode SET and RESET voltages are respectively supplied on the base ports of said transistors.

A Schmitt trigger circuit, comprising:

• a plurality of transistors, each emitter of said transistors is connected to a common current source, and
• negative differential resistance diodes which are respectively connected to collector of said transistors;
• the collector terminals of said transistors respectively serving as non-inverted and inverted output terminals;
• wherein the circuit satisfies the following relationships:
• V
• TH
• =
• η
• ⁢
• ⁢
• V
• T
• ⁢
• ln
• ⁡
• (
• I
• EE
• I
• V
• -
• 1
• )
• +
• V
• ⁢
• REF
• V
• TL
• =
• η
• ⁢
• ⁢
• V
• T
• ⁢
• ln
• ⁡
• (
• I
• EE
• I
• P
• -
• 1
• )
• +
• V
• ⁢
• REF
• where
• VTH,VTL:
• threshold voltages of the Schmitt trigger circuit,
• η:
• ideality factor of said transistors,
• VT:
• thermal voltage,
• IEE:
• the current of the current source connected in series to the common node of emitters of said transistors,
• IV:
• the valley current of said negative differential resistance diode,
• IP:
• the peak current of said negative differential resistance diode,
• wherein single or differential outputs are provided when VIN and VREF are respectively supplied as each base of said transistors.

A MOBILE based D-type flip flop, comprising:

• negative differential resistance diodes receiving a common clock signal, and commonly biased negative differential resistance diodes respectively connected to said negative differential resistance diodes receiving the common clock signal, and
• transistors, wherein each collector of the transistors is respectively connected between one of said negative differential resistance diodes receiving the common clock signal and between one of said commonly biased negative differential resistance diodes and, each emitter is connected to a common current source, and each base comprises an input port;
• and
• the flip-flop is configured to be operated in a Non-Return-to-Zero mode, in which each collector of said transistors is respectively connected to the base of a transistor for a SET/RESET latch circuit, and an output port is connected to the collector of said SET/RESET latch circuit.