Pseudo-random test generator in an integrated circuit
AssigneeCPU Technology, Inc.
InventorAlan Smith
Life of this patent
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Abstract
An integrated circuit with a multiplexer system and a control circuit is described. The multiplexer system has an output terminal connected to an output pin of the integrated circuit and input terminals connected to internal nodes of the integrated circuit. In a normal mode the control circuit generates the control signals so that any one of the internal nodes is connected to the output pin so that the integrated circuit can function flexibly. In a test mode so that a different internal node is connected to the output pin in each cycle of a test clock signal.
Claims23
An integrated circuit comprising
- a multiplexer system having at least one output terminal connected to at least one output pin of said integrated circuit and a plurality of input terminals connected to a plurality of internal nodes of said integrated circuit, said multiplexer system selectively connecting one of said plurality of internal nodes to said output pin responsive to control signals;
- and
- a control circuit generating said control signals to said multiplexer system so that a different internal node is sequentially connected to said at least one output pin responsive to a test clock signal.
An integrated circuit comprising
- a multiplexer system having at least one output terminal connected to at least one output pin of said integrated circuit and a plurality of input terminals connected to a plurality of internal nodes of said integrated circuit;
- and
- a control circuit generating said control signals to said multiplexer system so that at least one of said plurality of internal nodes is connected to said at least one output pin responsive to control signals in a normal mode and a different internal node is sequentially connected to said at least one output pin responsive to a test clock signal in a test mode.
A method of operating an integrated circuit comprising
- selectively connecting at least one of a plurality of internal nodes of said integrated circuit to at least one output pin of said integrated circuit through a multiplexer system in a normal mode;
- and
- sequentially connecting a different at least one of said plurality of internal nodes of said integrated circuit to said at least one output pin through said multiplexer system responsive to a test clock signal in a test mode.
Dependencies are inferred from the claim text.