Flash memory device with reduced access time

A flash memory device, comprising:

• a Finite State Machine (FSM) check unit, which detects and corrects error of an input data signal, a command signal, a write address signal and a read address signal, while decoding any one of the signals, to output one of a decoded input data signal, a decoded command signal, a decoded write address signal and a decoded read address signal, and detects and corrects error of a read data signal, state information and chip information, while encoding one of the read data signal, the state information and the chip information, to output one of an encoded read data signal, encoded state information and encoded chip information;
• and
• a flash memory core, which stores the decoded input data signal in response to the decoded command signal and the decoded write address signal, outputs the read data signal in response to the decoded command signal and the decoded read address signal, and outputs the state information and the chip information in response to a control signal.