Flash gate stack notch to improve coupling ratio
OwnerMichael Smaylinginventor
Life of this patent
Estimating the term…
Abstract
A semiconductor flash memory device with increased gate coupling ratio and a method of preparing this flash memory device. The semiconductor flash memory device includes a notched floating polysilicon gate. The notches are at the interface between the floating polysilicon layer and the tunneling dielectric layer. The notches reduce the capacitance between the floating polysilicon and the channel region. The reduced capacitance results in the increased gate coupling ratio. The degree of capacitance reduction, which affects the gate coupling ratio increase, is controlled by the width of the notches. The floating polysilicon gate etch includes a first anisotropic etch and a second isotropic etch. The widths of the notches are controlled by the etch time of the isotropic etch.
Claims23
A method of increasing the gate coupling ratio of a semiconductor flash memory cell, comprising:
- depositing a tunneling dielectric film on said semiconductor substrate;
- depositing a first gate film on said tunneling dielectric film;
- depositing an interlayer dielectric film on said first gate film;
- depositing a second gate film on said interlayer dielectric film;
- patterning the semiconductor substrate after the second gate film is deposited;
- etching the second gate film and the interlayer dielectric film;
- etching the first gate film to leave notches at a shared surface area with the tunneling dielectric film and at the edge of the cell;
- and
- etching the tunneling dielectric film.
Dependencies are inferred from the claim text.