Meander metal line under the pad for improved device MM ESD performance

A method for enhancing ESD protection of integrated circuit devices comprising:

• providing a partially processed semiconductor chip having product devices and ESD protection device and, under an I/O pad area, product device metal levels and ESD protection device metal levels;
• forming a multiplicity of layers containing a resistor whose lower end connects to said ESD protection device metal levels and whose upper end connects to pins of an I/O pad;
• forming top metal levels and said I/O pad above said top metal levels.

A method for enhancing ESD protection of integrated circuit devices comprising:

• providing a partially processed semiconductor chip having product devices and ESD protection device and, under an I/O pad area, product device metal levels and ESD protection device metal levels;
• forming a multiplicity of meander levels of meandering conductive lines separated from each other and from metal levels below and above by dielectric layers, with the lowest said meander level line connected to said ESD protection device metal levels, with said meandering conductive lines of said multiplicity of said meander levels connected in series to form a meander line series and with the line of the top meander level connected to top metal levels that lead to pins of an I/O pad, all connections being through the intervening dielectric levels;
• forming said top metal levels and said I/O pad disposed over said top metal levels.