Duty detection circuit and method for controlling the same

A duty detection circuit for detecting a duty of a clock signal and generating a duty correction signal based on the duty, the duty detection circuit comprising:

• a main circuit unit that includes at least a first capacitor that is discharged during the time period in which the clock signal is at a high level and charged during the time period in which the clock signal is at a low level, and a second capacitor that is charged during the time period in which the clock signal is at a high level and discharged during the time period in which the clock signal is at a low level, with the main circuit unit alternately charging or discharging the first and second capacitors in synchrony with the clock signal;
• and
• a duty correction signal generator for detecting the potential difference of the first and second capacitors and outputting a duty correction signal based on the potential difference.