US 2006/0232300 A1 · Semiconductor integrated circuit device manufacturing method

Abstract

To reduce variation in channel lengths of MOS transistors within a circuit functional module. When exposure of a wafer substrate having a semiconductor integrated circuit device 1 including a plurality of CMOS circuit module regions CCM11 to CCM22 to be subject to substrate bias control formed in a core region 10 is performed using a step-and-scan type projection exposure apparatus, scanning is performed in the same direction as a longitudinal direction of the respective CMOS circuit module regions CCM11 to CCM22. In this device, a gate insulating film is formed on the substrate, a gate electrode material film is formed on the gate insulating film, and a photoresist film is formed on the gate electrode material film.

Claims4

Dependent claims

A semiconductor integrated circuit device manufacturing method comprising the steps of:

(a) providing a wafer substrate including a semiconductor integrated circuit device having a plurality of CMOS circuit module regions formed in a core region thereof, said CMOS circuit module regions being subject to substrate bias control, said semiconductor integrated circuit device being configured to include a gate insulating film formed on said substrate, a gate electrode material film formed on said gate insulating film, and a photoresist film formed on said gate electrode material film;
and
(b) exposing said water substrate using a step-and-scan type projection exposure apparatus;
wherein upon said exposing, scanning is performed in a same direction as a longitudinal direction of each of said CMOS circuit module regions in said core region.

1 more element

Dependencies are inferred from the claim text.

Semiconductor integrated circuit device manufacturing method

Life of this patent

Semiconductor integrated circuit device manufacturing method

Life of this patent

Abstract

Claims4