Semiconductor wafer, semiconductor chip and dicing method of a semiconductor wafer

A method for dicing a semiconductor wafer having:

• a plurality of chip areas in which a number of semiconductor elements are formed;
• a dicing area provided at the outside of each chip area;
• a characteristic evaluating element formed in the dicing area;
• and
• a metal wiring formed in the dicing area and electrically connected to the characteristic evaluating element;
• this method including a step of relatively moving a blade along a longitudinal direction of the dicing area for cutting a portion of the dicing area out,
• wherein a coordinate axis Y is defined by a dicing center line, a coordinate axis X is defined by a direction perpendicular to the dicing center line, D is defined by a thickness of a cutting edge of the blade and ±σ is defined by a relative positioning error between the dicing blade and the semiconductor wafer in the direction of X and, in case where the dicing area is demarcated into five areas that are an area A (−D/2+σ<x<D/2−σ), an area B1 (−D/2−σ<x<−D/2+σ), an area B2 (D/2−σ<x<D/2+σ), an area C1 (x<−D/2−σ) and an area C2 (D/2+σ<x), the metal wiring is exposed in any one of areas of A, C1 and C2 while the metal wiring is not exposed in the areas B1 and B2.