Programmable and erasable digital switch device and fabrication method and operating method thereof

A programmable and erasable digital switch device, comprising:

• a substrate;
• a first conductive type well disposed within the substrate;
• a first stacked gate structure and a second stacked gate structure disposed on the substrate, the first stacked gate structure comprising a first charge storage layer and a first control gate, the second stacked gate structure comprising a second charge storage layer and a second control gate, the first control gate being electrically coupled to the second control gate;
• a first conductive type first doped region and a first conductive type second doped region disposed in the substrate adjacent to two sides of the first stacked gate structure respectively;
• and
• a second conductive type first doped region and a second conductive type second doped region disposed within the substrate adjacent to one of two sides of the second stacked gate structure respectively, wherein the second conductive type first doped region surrounds the first conductive type second doped region, and extends under the first stacked gate structure.

A method of fabricating a programmable and erasable digital switch device, comprising:

• providing a substrate;
• forming a first stacked gate structure and a second stacked gate structure on the substrate, the first stacked gate structure comprising a first tunnelling dielectric layer, a first charge storage layer, a first inter-gate dielectric layer and a first control gate, the second stacked gate structure comprising a second tunnelling dielectric layer, a second charge storage layer, a second inter-gate dielectric layer and a second control gate, the first control gate being electrically coupled to the second control gate;
• forming a first conductive type first doped region within the substrate between the first stacked gate structure and the second stacked gate structure, the first conductive type first doped region extending under the first stacked gate structure;
• forming a second conductive type first doped region and a second conductive type second doped region within the substrate adjacent to two sides of the first stacked gate structure, wherein the first conductive type first doped region surrounds the second conductive type second doped region;
• and
• forming a first conductive type second doped region within the substrate outside the second stacked gate structure.

A method of operating a programmable and erasable digital switch device, the programmable and erasable digital switch device comprising:

• an first conductive type memory transistor at least comprising a first conductive type first doped region, a first conductive type second doped region, a first charge storage layer and a first control gate;
• a second conductive type memory transistor at least comprising a second conductive type first doped region, a second conductive type second doped region, a second charge storage layer and a second control gate;
• a common bit line electrically coupled to a common bit line doped region constituted by the first conductive first type doped region and the second conductive type second doped region;
• and a word line electrically connecting the first control gate and the second control gate;
• the method comprising:
• performing an erasure operation by injecting electrons into the first charge storage layer and the second charge storage layer so that the first conductive type memory transistor and the second conductive type memory transistor have positive threshold voltages.