Flash memory devices and methods of fabricating the same

A flash memory device comprising:

• at least one active region in a semiconductor substrate;
• a string-selection gate line that crosses over the active region;
• a ground-selection gate line that crosses over the active region;
• a plurality of wordlines that cross over the active region between the string-selection gate line and the ground-selection gate line;
• a common source region in the active region at a first side of the ground-selection gate line;
• a source line that is electrically connected to the common source region;
• and
• a first source spacer that crosses over a first top edge region of the common source region and a second source spacer that crosses over a second top edge region of the common source region, wherein a lower portion of the source line is between the first source spacer and the second source spacer.

A method of fabricating a flash memory device, comprising:

• sequentially forming a gate insulation film, a preliminary floating gate, a blocking insulation film, and a first conductive film on a semiconductor substrate;
• patterning the first conductive film, the blocking insulation film and the preliminary floating gate to form a source opening that exposes the semiconductor substrate;
• injecting impurity ions into the semiconductor substrate exposed by the source opening to form a common source region;
• forming a first source spacer on a first sidewall of the source opening and forming a second source spacer on a second sidewall of the source opening;
• forming a second conductive film on the semiconductor substrate between the source spacers, wherein the second conductive film is electrically connected to the common source region;
• and
• patterning the second conductive film, the first conductive film, the blocking insulation film, and the preliminary floating gate using the source spacers as etch-stopping layers to form a string-selection gate line, a plurality of wordlines, a ground-selection gate line and a source line, wherein the source line is formed in a region between an outside wall of the first source spacer and an outside wall of the second source spacer.