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US 2006/0223304 A1Published application
Semiconductor device and pattern generating method
AssigneeFujitsu Limited
InventorsMasato Suga, Satoshi Otsuka
Life of this patent
Estimating the term…
Abstract
A first dummy pattern is arranged in the region allowed to generate the first dummy pattern, after that, the second dummy pattern is generated in the region not allowed to generate the first dummy pattern but allowed to generate the second dummy pattern to thereby enable to arrange the dummy patterns in an efficient manner in the wiring layer, so that the wiring density can be improved and differences in the wiring densities can be reduced.
Claims8
A pattern generation method comprising:
- a first dummy pattern arrangement step including arranging first dummy patterns by generating the first dummy patterns in a region allowed to generate the first dummy pattern based on a layout data having actual patterns arranged on a wiring layer in a semiconductor device;
- and
- a repeated step including repeating a kth dummy pattern arrangement step by incrementally changing a value of k, said kth dummy pattern arrangement step including arranging kth dummy patterns by generating the kth dummy patterns being different from the first to the (k-1)th (k is a natural number from 2 to N, N is optional.) dummy patterns in a region allowed to generate the kth dummy pattern based on the layout data having actual patterns and the first to the (k-1)th dummy patterns arranged on the wiring layer.
A pattern generation method comprising:
- a first dummy pattern arrangement step including arranging first dummy patterns by generating the first dummy patterns in a region allowed to generate the first dummy pattern, based on a layout data having an actual pattern arranged on a wiring layer in a semiconductor device;
- and
- a second dummy pattern arrangement step including arranging second dummy patterns by generating the second dummy patterns in a region allowed to generate the second dummy pattern based on the layout data having the actual pattern and the first dummy pattern arranged on the wiring layer, the second dummy pattern being a dummy pattern different from the first dummy pattern.
Dependencies are inferred from the claim text.