Method of production of charge-trapping memory devices

A method for producing a charge-trapping memory device, the method comprising:

• providing a semiconductor body;
• forming a memory layer sequence adjacent the semiconductor body, the memory layer sequence including dielectric materials provided for charge-trapping;
• forming a gate dielectric adjacent the semiconductor body;
• forming wordline stacks adjacent the memory layer sequence in a memory array area and forming gate electrodes adjacent the gate dielectric in the peripheral area of an addressing circuitry;
• implanting source/drain regions in said memory array area self-aligned to said wordline stacks;
• applying an oxynitride liner over the peripheral area and the memory array area;
• forming sidewall spacers along sidewalls of the gate electrodes in said peripheral area and filling interspaces between the wordline stacks in the area of the array of memory cells;
• implanting source/drain regions in said peripheral area using said sidewall spacers as masks in the memory array area;
• and
• filling interspaces between said gate electrodes with a dielectric material.