Back to results
US 2006/0223261 A1Published application
CMOS-based low ESR capacitor and ESD-protection device and method
AssigneeCalifornia Micro Devices Corporation
InventorsJohn Jorgensen, Harry Gee
Life of this patent
Estimating the term…
Abstract
A method for fabricating a low dynamic resistance capacitor is an integrated circuit using conventional CMOS processing steps, where in one implementation the structure provides the additional feature of a Zener diode capable of offering ESD protection.
Claims4
A method for fabricating a capacitor in an integrated circuit comprising the steps of
- providing a substrate having a first dopant concentration and an epitaxial layer thereon at a relatively lower dopant concentration,
- forming by conventional CMOS process, in the epitaxial layer, a third dopant region having a dopant concentration higher than the dopant concentration in the epitaxial layer and substantially the same dopant concentration as the first dopant concentration,
- causing the third dopant region to be driven into electrical connection with the substrate,
- forming an oxide layer over the third region through conventional CMOS processing,
- forming a metal layer over at least a portion of the oxide layer, and
- providing contacts to the metal layer and the substrate such that the metal layer, oxide and substrate form a capacitor operable at frequencies up to on the order of three Gigahertz.
3 more elements
A method for fabricating ESD protection in an integrated circuit comprising the steps of
- providing a substrate having a first dopant concentration and an epitaxial layer thereon at a relatively lower dopant concentration,
- forming by conventional CMOS process, in the epitaxial layer, a third dopant region having a dopant concentration higher than the dopant concentration in the epitaxial layer and substantially the same dopant concentration as the first dopant concentration,
- causing the third dopant region to be driven into electrical connection with the substrate,
- forming, within the third dopant region, a fourth dopant region of a characteristic opposite to the characteristic of the third dopant region,
- forming a metal layer over at least a portion of the oxide layer, and
- providing contacts to the metal layer and the substrate such that the metal layer, oxide and substrate from a Zener diode with low series resistance.
3 more elements
Dependencies are inferred from the claim text.