Method of fabricating a semiconductor device having CMOS transistors and a bipolar transistor
AssigneeNEC Electronics Corporation
InventorMototsugu Okushima
Life of this patent
Estimating the term…
Abstract
To reduce electric current concentration and electric field concentration in junction parts even in the case of miniaturization, and to achieve triggering at low voltage, an ESD protection apparatus is installed between an input terminal of a semiconductor integrated circuit chip and a CMOS transistor. The ESD protection apparatus includes a trigger element having diodes which are broken down by overvoltage applied to the input terminal and an ESD protection element including vertical bipolar transistors for discharging the accumulated electric charge of the input terminal by being electrically discharged owing to the breakdown of the diodes.
Claims6
A method for fabricating a semiconductor integrated circuit comprising:
- a first step of simultaneously forming an N− type well of a CMOS transistor comprising an inner circuit and an N− type well for collector connection to be connected with a collector of a vertical bipolar transistor on a P type silicon substrate;
- a second step of simultaneously forming a collector N− type well to be a collector of said vertical bipolar transistor and an N− type well of a diode on said P type silicon substrate;
- a third step of simultaneously forming a P− type layer to be a base in the collector N− type well of said vertical bipolar transistor and a P− type layer to be an anode in the N− type well of said diode;
- a fourth step of simultaneously forming an N+ type layer in the P− type well of said CMOS transistor, an N+ type layer in the N− type well for collector connection of said vertical bipolar transistor, an N+ type layer to be an emitter in the P− type layer of said vertical bipolar transistor, and an N+ type layer to be a cathode in the P− type layer of said diode;
- and
- a fifth step of simultaneously forming a P+ type layer on the N− type well of said CMOS transistor, a P+ type layer on the P− type layer of said vertical bipolar transistor, and a P+ type layer on the P− type layer of said diode.
A method for fabricating a semiconductor integrated circuit comprising:
- a first step of simultaneously forming an N− type well of a CMOS transistor constituting an inner circuit and an N−type well for collector connection to be connected with a vertical bipolar transistor on a P type silicon substrate;
- a second step of simultaneously forming a collector N− type well to be a collector of said vertical bipolar transistor and the N− type well of a diode on said P type silicon substrate;
- a third step of simultaneously forming a P−type layer to be a base in the collector N−type well of said vertical bipolar transistor and the P−type layer to be a cathode in the N−type well of said diode;
- a fourth step of simultaneously forming an N+layer in the P−type well of said CMOS transistor, the N+layer in the N−type well for collector connection of said vertical bipolar transistor, the N+layer to be an emitter in the P−type layer of said vertical bipolar transistor, and the N+layer to be an anode in the P−type layer of said diode;
- and
- a fifth step of simultaneously forming the P+layer in the N−type well of said CMOS transistor, the P+layer in the P−type layer of said vertical bipolar transistor and the P+layer in the P−type layer of said diode.
A method for fabricating a semiconductor integrated circuit having CMOS transistors and a bipolar transistor comprising:
- simultaneously forming an N−type first well for PMOS transistor and an N− type second well for collector connection to be connected with a collector of a bipolar transistor on a P type semiconductor substrate;
- providing a first mask layer above said semiconductor sebstrate, said first mask layer having a first opening;
- forming a collector N− type well to be a collector of said bipolar transistor in said semiconductor substrate based on a shape of said first opening;
- forming a P− type first layer to be a base of said bipolar transistor on said collector N− type third well based on said shape of said first opening;
- simultaneously forming an N+ type source-drain region of a NMOS transistor on said P type semiconductor substrate, an N+ type layer in said N− type well for collector connection of said bipolar transistor, an N+ type layer to be an emitter in the P− type later of said bipolar transistor;
- and
- simultaneously forming a P+ type source-drain region of PMOS transistor on said N− type well, and a P+ type base connecting region on said P− type layer to be a base region.
Dependencies are inferred from the claim text.