Semiconductor device and designing method for the same
AssigneeSeiko Instruments Inc.
InventorSumio Koiwa
Life of this patent
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Abstract
Provided is a semiconductor electrostatic discharge protection device with a high tolerance for an electrostatic discharge without increase in manufacturing cost and degradation in performance of a semiconductor device. Conductors are arranged over a semiconductor circuit formed on a semiconductor substrate, a part of the conductors are connected to a power supply line, and the rest of the conductors are connected to a ground line, in order to enhance the tolerance for the electrostatic discharge in an air discharge model. Further, an areal ratio of the conductors with respect to the semiconductor circuit is set at 40% or more, thereby forming a semiconductor electrostatic discharge protection device with excellent efficiency.
Claims5
A semiconductor device, comprising:
- a semiconductor circuit provided on a semiconductor substrate;
- and
- conductors for electrostatic discharge protection disposed over the semiconductor circuit, and having a ratio of a total area of the conductors disposed over the semiconductor circuit to an area of a chip occupied by the semiconductor circuit being 40% or more.
A method of designing a semiconductor device, comprising:
- providing a plurality of conductors for protecting a semiconductor element included in a semiconductor circuit from an electrostatic discharge breakdown, over the semiconductor circuit formed on a semiconductor substrate;
- connecting a part of the conductors to a power supply line to use the part of the conductors as VDD protection conductors, and connecting the protection conductors which are not connected to the power supply line to a ground line to use the protection conductors as GND protection conductors;
- and
- adjusting a ratio of a total area of the VDD protection conductors to a total area of the GND protection conductors to determine a tolerance for an ESD.
Dependencies are inferred from the claim text.