Clock delay compensation circuit
AssigneeFreescale Semiconductor, Inc.
InventorsNitin Vig, Amab Mitra
Life of this patent
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Abstract
A clock delay compensation circuit for an integrated circuit having a first voltage domain and a second voltage domain, has a first delay element that receives a clock signal and generates a first delayed clock signal, and a multiplexer that receives the clock signal and the first delayed clock signal and generates a variable clock signal. The first delayed clock signal is selected when the second voltage domain is at a higher voltage level than the first voltage domain.
Claims20
A clock delay compensation circuit for an integrated circuit having at least a first voltage domain and a second voltage domain, the clock delay compensation circuit comprising:
- a first delay element that receives a clock signal and generates a first delayed clock signal;
- and
- a multiplexer that receives the clock signal and the first delayed clock signal and generates a variable clock signal, wherein the first delayed clock signal is selected when the second voltage domain is at a higher voltage level than the first voltage domain.
A clock delay compensation circuit for an integrated circuit having a first, constant voltage domain and a second, variable voltage domain, wherein the first voltage domain operates in accordance with a substantially constant clock signal and the second voltage domain operates in accordance with a variable clock signal, the clock delay compensation circuit comprising:
- a first delay element that receives the substantially constant clock signal and generates a first delayed clock signal;
- and
- a multiplexer that receives the substantially constant clock signal and the first delayed clock signal and generates the variable clock signal, wherein the first delayed clock signal is selected when the second voltage domain is at a higher voltage level than the first voltage domain.
Dependencies are inferred from the claim text.