E-Fuse and anti-E-Fuse device structures and methods
AssigneeInternational Business Machines Corporation
InventorsJeffrey Brown, Robert Gauthier, Jed Rankin, William Tonti
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AssigneeInternational Business Machines Corporation
InventorsJeffrey Brown, Robert Gauthier, Jed Rankin, William Tonti
Estimating the term…
Standard photolithography is used to pattern and fabricate a final polysilicon wafer imaged structure which is smaller than normal allowable photo-lithographic minimum dimensions. Three different methods are provided to produce such sub-minimum dimension structures, a first method uses a photolithographic mask with a sub-minimum space between minimum size pattern features of the mask, a second method uses a photolithographic mask with a sub-minimum widthwise jog or offset between minimum size pattern features of the mask, and a third method is a combination of the first and second methods. Each of the three methods can be used with three different embodiments, a first embodiment is a polysilicon E-Fuse with a sub-minimum width polysilicon fuse line, a second embodiment is a work function altered/programmed self-aligned MOSFET E-Fuse with a sub-minimum width fuse line, and a third embodiment is a polysilicon MOSFET E-Fuse with a sub-minimum width fuse line which is programmed with a low trigger voltage snapback.
A fuse element formed on a semiconductor substrate, the substrate having a subset of integrated circuit elements thereon having a minimum normal design width which is smaller than the width of other integrated circuit elements on said substrate and that receive first and second power supply voltages, a conductive line formed on said substrate and having two end portions and a center portion of said minimum normal design width, and a link portion within said center portion and spaced from said end portions which has a sub-minimum width less than said minimum normal design width, wherein an application of said first and second power supply voltages across said end portions causes an electrical property of said fuse element to undergo a detectable change.
A mask used to form a sub-minimum image, comprising a first minimum size feature, and a second minimum size feature that is offset and spaced from said first minimum size feature.
A process of forming a sub-minimum size feature on a substrate, comprising:
Dependencies are inferred from the claim text.