Trench isolation structures for semiconductor devices and methods of fabricating the same

A method of forming a trench isolation structure in a semiconductor device, the method comprising:

• defining a cell region, a low voltage region and a high voltage region in a semiconductor substrate;
• etching the semiconductor substrate in the high voltage region to form a recess;
• simultaneously etching portions of the substrate in the low voltage region and the recess to form a low voltage trench in the low voltage region and a high voltage trench deeper than the low voltage trench in the high voltage region;
• simultaneously etching portions of the substrate in the cell region, the low voltage trench region and the high voltage trench to form a cell trench in the cell region and to deepen the low voltage trench in the low voltage region and the high voltage trench in the high voltage region;
• and
• filling the cell trench, the low voltage trench and the high voltage trench with insulating material to form a trench isolation structure comprising a cell trench isolation region in the cell region, a low voltage trench isolation region in the low voltage region, and a high voltage trench isolation region in the high voltage region.

A method for forming a trench isolation structure of a semiconductor device, the method comprising:

• defining a cell region, a low voltage region and a high voltage region in a semiconductor substrate;
• forming a gate insulating layer on the cell region, the low voltage region and the high voltage region, wherein the gate insulating layer in the high voltage region is thicker than the gate insulation layer in the low voltage region;
• forming a mask layer on the gate insulating layer;
• patterning the mask layer and the gate insulating layer to form a mask pattern that exposes portions of the substrate in the cell region and the high voltage region;
• forming a resist pattern that covers the exposed portion of the substrate in the cell region and exposes a portion of the mask layer in the low voltage region and a portion of the substrate in the high voltage region;
• etching the exposed portions of the mask pattern and the substrate using the resist pattern as an etch mask to form a recess in the high voltage region and to expose portion of the substrate in the low voltage region;
• removing the resist pattern to expose a portion of the substrate in the cell region;
• etching exposed portions of the substrate exposed in the cell region, the low voltage region and the high voltage region to form a cell trench in the cell region, a low voltage trench deeper than the cell trench in the low voltage region, a first high voltage trench deeper than the low voltage trench and a second high voltage trench in the high voltage region that is deeper than the low voltage trench and shallower than the first high voltage trench;
• and
• forming insulating regions in the cell trench, the low voltage trench and the first and second high voltage trenches.

A method of forming a trench isolation structure of a semiconductor device, the method comprising:

• defining a cell region, a low voltage region and a high voltage region in a semiconductor substrate;
• forming a gate insulating layer on the cell region, the low voltage region and the high voltage region, wherein the gate insulating layer formed on the high voltage region is thicker than on the low voltage region;
• forming a mask layer on the gate insulating layer;
• patterning the mask layer and the gate insulating layer to form a mask pattern that exposes portions of the substrate in the cell region and the high voltage region;
• forming a resist pattern that covers the portion of the substrate exposed in the cell region, that exposes portions of the mask layer in the low voltage region and the high voltage region, and that exposes a portion of the substrate in the high voltage region and a portion of the mask layer around the exposed portion of the substrate;
• etching the exposed portions of the mask pattern and the substrate using the resist pattern as an etch mask to form a recess in the high voltage region and to expose portions of the substrate in the high voltage region and the low voltage region;
• simultaneously etching the exposed portions of the substrate in the high voltage region, the low voltage region and the recess using the resist pattern as an etch mask to form a first high voltage trench in the recess, a second high voltage trench in the high voltage region and a low voltage trench in the low voltage region;
• removing the resist pattern to expose a portion of the substrate in the cell region;
• etching exposed portions of the substrate in the cell region, the high voltage region and the low voltage region to form a cell trench in the cell region and to deepen the low voltage trench, the first high voltage trench and the second high voltage trench, such that the low voltage trench is deeper than the cell trench, the second high voltage trench is deeper that the low voltage trench, and the first low voltage trench is deeper than the second high voltage trench;
• and
• forming insulating regions in the cell trench, the low voltage trench and the first and second high voltage trenches.

A method for forming a trench isolation structure of a semiconductor device, the method comprising:

• defining a cell region, a low voltage region and a high voltage region in a semiconductor substrate;
• forming a gate insulating layer in the cell region, the low voltage region and the high voltage region, the gate insulating layer on the high voltage region thicker than on the low voltage region;
• forming a mask layer on the gate insulating layer;
• patterning the mask layer and the gate insulating layer to form a mask pattern that exposes portions of the substrate in the cell region and the high voltage region;
• forming a resist pattern that covers the exposed portion of the substrate in the cell region, that partially covers the exposed portion of the substrate in the high voltage region and that exposes portions of the mask pattern in the low voltage region and the high voltage region;
• etching exposed portions of the substrate and the mask region using the resist pattern as an etch mask to form a recess in the high voltage region and to expose portions of the substrate in the high voltage region and the low voltage region;
• etching the exposed portions of the substrate in the high voltage region, the low voltage region and the recess using the resist pattern as an etch mask to form a low voltage trench in the low voltage region, a first high voltage trench at the recess and a second high voltage trench in the high voltage region;
• removing the resist pattern to expose a portion of the substrate in the cell region and a portion of the substrate around the high voltage trench;
• and
• etching the exposed portion of the substrate in the cell trench, the low voltage trench and the first and second high voltage trenches to form a cell trench in the cell region and to deepen the low voltage trench and the first and second high voltage trenches such that the low voltage trench is deeper than the cell trench, the second high voltage trench is deeper than the low voltage trench, and the first high voltage trench is deeper than the second high voltage trench;
• and
• forming insulating regions in the cell trench, the low voltage trench and the first and second high voltage trenches.