Electrostatic discharge input protection circuit
AssigneeHynix Semiconductor Inc.
InventorKwang-Myoung Rho
Life of this patent
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Abstract
An ESD protection circuit includes: a first metal oxide semiconductor (MOS) transistor discharging an excessive electrostatic current generated between an input pad and an internal circuit, and having a first terminal connected to a ground voltage supply terminal; and a second MOS transistor discharging an electrostatic current generated between the input pad and the internal circuit, and having a gate and a first terminal connected to a bulk terminal of the first MOS transistor. The first terminal is connected to the ground voltage supply terminal through an interconnection line having a parasitic resistance with a predetermined value.
Claims10
An electrostatic discharge (ESD) protection circuit, comprising:
- a first metal oxide semiconductor (MOS) transistor discharging an excessive electrostatic current generated between an input pad and an internal circuit, and having a first terminal connected to a ground voltage supply terminal;
- and
- a second MOS transistor discharging an electrostatic current generated between the input pad and the internal circuit, and having a gate and a first terminal connected to a bulk terminal of the first MOS transistor, wherein the first terminal is connected to the ground voltage supply terminal through an interconnection line having a parasitic resistance with a predetermined value.
An ESD protection circuit, comprising:
- a first MOS transistor discharging an excessive electrostatic current generated between an input pad and an internal circuit and having a first terminal connected to a ground voltage supply terminal;
- and
- a second MOS transistor discharging an electrostatic current generated between the input pad and the internal circuit, having a gate and a first terminal commonly connected to a bulk terminal and a gate terminal of the first MOS transistor, wherein the first terminal is connected to the ground voltage supply terminal through an interconnection line having a parasitic resistance with a predetermined value.
An ESD protection circuit, comprising:
- a first MOS transistor discharging an excessive electrostatic current generated between an input pad and an internal circuit, and having a first terminal connected to a ground voltage supply terminal;
- a second MOS transistor discharging an electrostatic current generated between the input pad and the internal circuit, and having a gate and a first terminal connected to a bulk terminal of the first MOS transistor, wherein the first terminal is connected to the ground voltage supply terminal through an interconnection line having a parasitic resistance with a predetermined value;
- and
- a third MOS transistor discharging an electrostatic current generated between the ground voltage supply terminal and a power voltage supply terminal, and having a bulk terminal connected to the first terminal of the second MOS transistor.
An ESD protection circuit, comprising:
- a first MOS transistor discharging an excessive electrostatic current generated between an input pad and an internal circuit, and having a first terminal connected to a power voltage supply terminal;
- and
- a second MOS transistor discharging an electrostatic current generated between the input pad and the internal circuit, and having a gate and a first terminal connected to a bulk terminal of the first MOS transistor, wherein the first terminal of the first MOS transistor is connected to the power voltage supply terminal through an interconnection line having a parasitic resistance with a predetermined value.
An ESD protection circuit, comprising:
- a first MOS transistor discharging an excessive electrostatic current generated between an input pad and an internal circuit, and having a first terminal connected to a power voltage supply terminal;
- and
- a second MOS transistor discharging an electrostatic current generated between the input pad and the internal circuit, and having a gate and a first terminal commonly connected to a bulk terminal and a gate terminal of the first MOS transistor, wherein the first terminal of the first MOS transistor is connected to the power voltage supply terminal through an interconnection line having a parasitic resistance with a predetermined value.
Dependencies are inferred from the claim text.