Gate structures of a non-volatile memory device and methods of manufacturing the same

A method of manufacturing a gate structure of a non-volatile memory device comprising:

• forming a tunnel insulating layer on a substrate;
• forming a charge trapping layer on the tunnel insulating layer;
• forming a composite dielectric layer on the charge trapping layer, the composite dielectric layer comprising a laminate structure in which a plurality of first material layers comprising aluminum oxide and a plurality of second material layers comprising a high-k material having a dielectric constant higher than that of the aluminum oxide are alternately stacked;
• forming a conductive layer on the composite dielectric layer;
• and
• patterning the conductive layer, the composite dielectric layer, the charge trapping layer, and the tunnel insulating layer so as to form the gate structure comprising a tunnel insulating layer pattern, a charge trapping layer pattern, a composite dielectric layer pattern, and a gate electrode.