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US 2006/0220086 A1Published application
IMOS transistor
AssigneeSTMicroelectronics (Crolles 2) SAS
InventorsClement Charbuillet, Thomas Skotnicki, Alexandre Villaret
Life of this patent
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Abstract
A vertical IMOS-type transistor including: a stack of a first semiconductor portion doped with dopant elements of a first type, of a second substantially undoped intrinsic semiconductor portion, and of a third semiconductor portion doped with dopant elements of a second type forming a PIN-type diode; and a conductive gate placed against the stack with an interposed insulating layer.
Claims10
A vertical IMOS-type transistor comprising:
- a conductive access area placed in a upper part of a substrate and surrounded with an insulating area;
- a stack of a first semiconductor portion doped with dopant elements of a first type, of a second substantially undoped intrinsic semiconductor portion, and of a third semiconductor portion doped with dopant elements of a second type forming a PIN-type diode, the stack being placed on the conductive access area, said third portion being placed on the top of the stack and partly extending above said insulating area;
- and
- a conductive gate placed against said stack with an interposed insulating layer.
1 more element
A method for forming a vertical IMOS transistor comprising the steps of:
- forming, at the surface of a semiconductor substrate, an insulating area which surrounds an area of the substrate called the lower area doped with dopant elements of a first type;
- forming an intrinsic semiconductor block above the lower area;
- forming a semiconductor layer doped with dopant elements of a second type which covers the intrinsic block and the insulating area;
- anisotropically etching the semiconductor layer, the intrinsic block, and the surface portion of said lower area whereby a stack of a “lower” portion doped with elements of the first type, of an intrinsic portion, and of an upper semiconductor portion doped with dopant elements of the second type is formed, the upper semiconductor portion extending above said insulating area;
- conformally depositing a thin insulating layer);
- conformally depositing a conductive layer;
- and
- anisotropically etching the conductive layer and the thin insulating layer, whereby conductive spacers are formed against said stacking and against the sides of the parts of the upper portion placed above the insulating area and a conductive block is formed in contact with spacers placed above said insulating layer.
5 more elements
Dependencies are inferred from the claim text.