Semiconductor device having a dummy gate
AssigneeElpida Memory, Inc.
InventorKazuhiro Yoshida
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a plurality of MOS transistors, wherein each of the MOS transistors has a drain region, a pair of source regions sandwiching therebetween the drain region, and a pair of normal gates each overlying a space between the drain region and a corresponding one of the source regions. A plurality of dummy gates are provided each between adjacent two of the MOS transistors. The dummy gate electrodes are maintained at an equi-potential with the adjacent drain regions. MOS transistors include a row of pMOS transistors and nMOS transistors, wherein each of pMOS transistors and a corresponding nMOS transistor configure a CMOS gate, and a plurality of CMOS gates configure a ring oscillator.
Claims10
A semiconductor device comprising:
- a semiconductor substrate;
- a plurality of MOS transistors arranged on said semiconductor substrate in a row and each including a drain region, a pair of source regions and a pair of normal gate electrodes, which are arranged in a direction of said row, said pair of source regions sandwiching therebetween said drain region, each of said pair of normal gate electrodes overlying a space between said drain region and a corresponding one of said source regions;
- and
- a plurality dummy gate electrodes each overlying a space between one of said source regions of one of said MOS transistors and one of said source regions of an adjacent one of said MOS transistors, each of said dummy gate electrodes being maintained at an equi-potential with said one of said source regions of said one or said adjacent one of said MOS transistors.
Dependencies are inferred from the claim text.