pHEMT with barrier optimized for low temperature operation

A method for forming a semiconductor device comprising:

• providing a substrate;
• forming a buffer layer over the substrate;
• forming a bottom layer, comprising AlxGa1-xAs, over the buffer layer, the bottom layer having a first doped region formed therein, wherein the first doped region comprises a first layer of GaAs, a monolayer of Si formed over the first layer of GaAs, and a second layer of GaAs formed over the monolayer of Si, wherein the first doped region is less than approximately 40 Å in thickness;
• forming an InxGa1-xAs channel layer over the bottom layer;
• forming an AlxGa1-xAs layer over the InxGa1-xAs layer, the AlxGa1-xAs layer having a second doped region formed therein, wherein the second doped region comprises a first layer of GaAs, a monolayer of Si formed over the first layer of GaAs, and a second layer of GaAs formed over the monolayer of Si, wherein the second doped region is less than approximately 40 Å in thickness;
• forming an undoped GaAs layer over the AlxGa1-xAs layer, the GaAs layer having a first recess formed therein that exposes a portion of the AlxGa1-xAs layer;
• forming a doped GaAs layer formed over the GaAs layer, the doped GaAs layer having a second recess therein that exposes a portion of the undoped GaAs layer;
• forming a control electrode having opposite ends within the first recess of the undoped GaAs layer and within the second recess of the doped GaAs layer;
• and
• forming first and second current electrodes disposed on the doped GaAs layer proximate opposite ends of the control electrode such that the doped GaAs layer provides current through the first and second current electrodes for the semiconductor device.

An amplifier comprising:

• a transistor comprising:
• a substrate;
• a buffer layer formed over the substrate;
• an AlxGa1-xAs layer formed over the buffer layer, the AlxGa1-xAs layer having a first doped region formed therein, wherein the first doped region comprises a layer of GaAs, a layer of Si, and a layer of GaAs;
• an InxGa1-xAs layer formed over the AlxGa1-xAs layer;
• an AlxGa1-xAs layer formed over the InxGa1-xAs layer, the AlxGa1-xAs layer having a second doped region formed therein, wherein the second doped region comprises a layer of GaAs, a layer of Si, and a layer of GaAs;
• an undoped GaAs layer formed over the AlxGa1-xAs layer, the undoped GaAs layer having a first recess formed therein that exposes a portion of the AlxGa1-xAs layer;
• a doped GaAs layer formed over the GaAs layer, the doped GaAs layer having a second recess therein that exposes a portion of the undoped GaAs layer;
• a control electrode having opposite ends formed within the first recess of the undoped GaAs layer and within the second recess of the doped GaAs layer;
• and
• first and second current electrodes disposed on the doped GaAs layer proximate opposite ends of the control electrode such that the doped GaAs layer provides current through the first and second current electrodes for the semiconductor device;
• a gate bias network coupled to the control electrode of the transistor;
• and
• a drain bias network coupled to the first current electrode.