Switch circuit, semiconductor device, and method of manufacturing said semiconductor device
AssigneeEudyna Devices Inc.
InventorHajime Matsuda
Life of this patent
Estimating the term…
Abstract
A switch circuit includes: a first FET that is connected to one of an input terminal and an output terminal, and performs ON/OFF operation under the control of a gate electrode connected to a control terminal; and a second FET that is connected between the first FET and the other one of the input terminal and the output terminal, and performs ON/OFF operation under the control of a gate electrode connected to the control terminal. The first FET has a higher gate backward breakdown voltage than that of the second FET. Alternatively, the first FET has lower OFF capacitance than that of the second FET.
Claims16
A switch circuit comprising:
- a first FET that is connected to one of an input terminal and an output terminal, and performs ON/OFF operation under the control of a gate electrode connected to a control terminal;
- and
- a second FET that is connected between the first FET and the other one of the input terminal and the output terminal, and performs ON/OFF operation under the control of a gate electrode connected to the control terminal,
- the first FET having a higher gate backward breakdown voltage than that of the second FET.
A switch circuit comprising:
- a first FET that is connected to one of an input terminal and an output terminal, and performs ON/OFF operation under the control of a gate electrode connected to a control terminal;
- and
- a second FET that is connected between the first FET and the other one of the input terminal and the output terminal, and performs ON/OFF operation under the control of a gate electrode connected to the control terminal,
- the first FET having lower OFF capacitance than that of the second FET.
A semiconductor device comprising:
- a first FET that is connected to one of an input terminal and an output terminal, and performs ON/OFF operation under the control of a gate electrode connected to a control terminal;
- and
- a second FET that is connected between the first FET and the other one of the input terminal and the output terminal, and performs ON/OFF operation under the control of a gate electrode connected to the control terminal,
- a part of the gate electrode being embedded in an embedding layer in each of the first FET and the second FET, an embedded thickness of the part of the gate electrode embedded in the embedding layer of the first FET being smaller than an embedded thickness of the part of the gate electrode embedded in the embedding layer of the second FET.
A semiconductor device comprising:
- a first FET that is connected to one of an input terminal and an output terminal, and performs ON/OFF operation under the control of a gate electrode connected to a control terminal;
- and
- a second FET that is connected between the first FET and the other one of the input terminal and the output terminal, and performs ON/OFF operation under the control of a gate electrode connected to the control terminal,
- the first FET and the second FET each having semiconductor layer surfaces covered with silicon nitride film between the gate electrode and a source electrode and between the gate electrode and a drain electrode, the silicon nitride film in the first FET having a lower nitrogen composition ratio than a nitrogen composition ratio of the silicon nitride film in the second FET.
A semiconductor device comprising:
- a first FET that is connected to one of an input terminal and an output terminal, and performs ON/OFF operation under the control of a gate electrode connected to a control terminal;
- and
- a second FET that is connected between the first FET and the other one of the input terminal and the output terminal, and performs ON/OFF operation under the control of a gate electrode connected to the control terminal,
- the first FET and the second FET each having the gate electrode in a gate recess, a gate recess width in the first FET being larger than a gate recess width in the second FET.
A method of manufacturing a semiconductor device that includes:
- a first FET that is connected to one of an input terminal and an output terminal, and performs ON/OFF operation under the control of a gate electrode connected to a control terminal;
- and a second FET that is connected between the first FET and the other one of the input terminal and the output terminal, and performs ON/OFF operation under the control of a gate electrode connected to the control terminal,
- the method comprising the steps of:
- forming an embedding layer on a Schottky layer on which the gate electrode is provided;
- selectively reducing the thickness of a portion of the embedding layer at which the gate electrode of the first FET is to be formed, by exposing the portion of the embedding layer at which the gate electrode of the first FET is to be formed and then covering a portion of the embedding layer at which the gate electrode of the second FET is to be formed with a mask layer;
- forming openings to expose the Schottky layer through the portions of the embedding layer at which the gate electrodes of the first FET and the second FET are to be formed;
- and
- forming the gate electrodes in the openings.
A method of manufacturing a semiconductor device that includes:
- a first FET that is connected to one of an input terminal and an output terminal, and performs ON/OFF operation under the control of a gate electrode connected to a control terminal;
- and a second FET that is connected between the first FET and the other one of the input terminal and the output terminal, and performs ON/OFF operation under the control of a gate electrode connected to the control terminal,
- the method comprising the steps of:
- forming a first silicon nitride film on a semiconductor layer;
- selectively removing the first silicon nitride film while leaving portions of the first silicon nitride film in regions to be located between the gate electrode and a source electrode and between the gate electrode and a drain electrode of the first FET and in regions to be located between the gate electrode and a source electrode and between the gate electrode and a drain electrode of the second FET;
- and
- forming a second silicon nitride film in the regions to be located between the gate electrode and the source electrode and between the gate electrode and the drain electrode of the first FET on the semiconductor layer, the second silicon nitride film having a lower nitrogen composition ratio than that of the first silicon nitride film.
Dependencies are inferred from the claim text.