Method for the recognition and/or correction of memory access error electronic circuit arrangement for carrying out said method

Abstract

Disclosed is a system and method for the detection and/or correction of memory access errors in computer systems. Test data (P) is generated in addition to data (D) which is to be secured, using the latter data (D), and is stored inside a memory (4) in such a fashion that a particularly high rate of reliability in error detection and correction can be achieved. To this end, in addition to the data (D) to be secured, the data's addresses are taken into account according to the present system and method when generating the test data (P).

Dependencies are inferred from the claim text.