Add-shift-round instruction with dual-use source operand for DSP

A SIMD processor adapted to execute instructions including an additive-shift-round instruction which includes an opcode field, a first SIMD source field, a second SIMD source field, and a dual-use field, the SIME processor comprising:

• means for retrieving (i) a first SIME operand including a plurality of first scalar operand values in response to contents of the first SIMD source field, and (ii) a second SIMD operand including a plurality of second scalar operand values in response to contents of the second SIMD source field;
• means for generating a shift control word and a rounding bias value in response to contents of the dual-use field;
• a SIMD additive execution unit for performing an additive operation specified by the opcode field upon corresponding ones of (i) the first scalar operand values, (ii) the second scalar operand values, and (iii) the rounding bias value, to generate a SIMD additive result including a plurality of scalar additive result values;
• a SIMD shift unit for shifting each of the scalar additive result values in response to the shift control word, to generate a SIMD shifted result including a plurality of scalar shifted result values;
• and
• means for storing the SIMD shifted result.

A processor for coupling to a memory, the processor comprising:

• a register file;
• an instruction fetcher coupled to receive instructions from the memory, the instructions including an add-shift-round instruction;
• an instruction decoder coupled to the instruction fetcher for decoding fetched instructions;
• an instruction scheduler coupled to the instruction decoder for scheduling decoded instructions for execution;
• a plurality of execution units coupled to the instruction scheduler and the register file for executing the scheduled instructions and writing results of the executed instructions to the register file, wherein the plurality of execution units includes,
• a dual-use-source ALU for executing the add-shift-round instruction, and including,
• an adder coupled to receive source operands, for adding the source operands to generate a sum,
• a shifter coupled to the adder for shifting the sum to generate a result, and
• logic coupled to receive a dual-use-source operand, the dual-use-source operand specifying one of a rounding addend and a shift count, for generating the other of the rounding addend and the shift count,.
• wherein the adder is coupled to receive the rounding addend from the logic, and the shifter is coupled to receive the shift count from the logic.

An improvement in a processor, the processor including means for retrieving source data operands and instructions, means for executing the instructions, and means for storing results of the executed instructions, wherein the improvement comprises:

• the processor having an ability to execute an instruction which specifies an operation, a plurality of source data operands, and an immediate value;
• wherein, the immediate value specifies one of a final source data value and a shift count;
• and
• the processor ability includes an ability to derive the other of the final source data value and the shift count, from the immediate value.

A method of processing data in a processor, comprising in the execution of a single instruction:

• receiving M source data values from sources specified by operands of the instruction;
• receiving an immediate value specified by an operand of the instruction;
• deriving one of a rounding bias value and a shift count from the immediate value, the immediate value specifying the other of the rounding bias value and the shift count;
• performing an arithmetic operation on the source data values and the rounding bias value to generate a result value;
• and
• shifting the result value by the shift count to generate a shifted result value.