BEOL integration scheme for etching damage free ELK

A semiconductor device fabrication method comprising:

• forming a set of interlevel wiring interconnect structures through a first dielectric layer, wherein the set comprises a conductive feature, an upper wiring level over the conductive feature, and a conductive via connecting the conductive feature and the upper wiring level;
• anisotropically etching the first dielectric layer using the upper wiring level as a mask such that substantially all the first dielectric layer is removed except for a residual dielectric underneath the upper wiring level;
• removing the residual dielectric with an isotropic etch;
• and
• filling substantially all space between adjacent interlevel wiring interconnect structures with a second dielectric layer.

A method for forming an interconnect structure comprising:

• forming a first dielectric layer on a substrate;
• forming a dual damascene structure through the first dielectric layer to the substrate, wherein the dual damascene structure comprises a trench, wherein the trench overlies a via and at least a portion of the first dielectric layer;
• forming a first recess by anisotropically etching the first dielectric layer using the trench as a mask;
• forming a second recess by isotropically etching a portion of the first dielectric layer underlying the trench;
• and
• forming a second dielectric layer by filling the first recess and the second recess with a second dielectric.