Smart grading implant with diffusion retarding implant for making integrated circuit chips

A method of making an N-channel transistor device, comprising:

• forming a spacer structure along sides of a gate structure, the gate structure being located on a substrate;
• performing a relatively high-energy low-dose implant, including ions selected from a group consisting of phosphorous and arsenic, into a source/drain region of the substrate between the spacer and an isolation region, wherein the high-energy low-dose implant is performed with an implant energy larger than about 15 keV and a dosage less than about 1×1015 dopants/cm2;
• performing a diffusion retarding implant, including ions selected from a group consisting of carbon and fluorine, into the source/drain region of the substrate, wherein the diffusion retarding implant is performed at an implant energy between about 2 keV and about 15 keV;
• and
• after performing the high-energy low-dose implant and the diffusion retarding implant, performing a relatively low-energy high-dose implant, including ions selected from a group consisting of phosphorous and arsenic, into the source/drain region of the substrate, wherein the low-energy high-dose implant is performed with an implant energy less than about 15 keV and a dosage greater than about 1×1015 dopants/cm2.

A method of making an integrated circuit chip, comprising:

• performing a relatively high-energy low-dose implant of ions into a source/drain region of a substrate;
• performing a diffusion retarding implant into the source/drain region of the substrate, wherein the diffusion retarding implant has a concentration percentage from about 1% to about 10% in the substrate;
• and
• after performing the high-energy low-dose implant and the diffusion retarding implant, performing a relatively low-energy high-dose implant of ions into the source/drain region of the substrate.