Manufacturing method of a flash memory cell

A method of fabricating a flash memory cell, comprising:

• providing a first conductive type substrate;
• forming a second conductive type shallow well in the first conductive type substrate;
• forming a stacked gate structure over the first conductive type substrate, wherein the stacked gate structure comprises a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate sequentially stacked over the first conductive type substrate and the stacked gate structure is disposed over the second conductive type shallow well;
• forming a first conductive type source region and a first conductive type drain region in the first conductive type substrate within the second conductive type shallow well on each side of the stacked gate structure;
• forming a metal silicide layer within the first conductive type drain region;
• forming a doped region underneath the metal silicide layer such that the doped region connects electrically with the metal silicide layer and passes through the junction between the first conductive type drain region and the second conductive type shallow well;
• forming an inter-layer dielectric layer over the first conductive type substrate and the stacked gate structure, wherein the inter-layer dielectric layer has an opening that exposes a portion of the first conductive type drain region;
• and
• forming a contact plug inside the opening of the inter-layer dielectric layer such that the contact plug is electrically connected to the first conductive type drain and the second conductive type shallow well through the metal silicide layer and the doped region.

A method of fabricating a flash memory cell, comprising:

• providing a first conductive type substrate;
• forming a second conductive type shallow well in the first conductive type substrate;
• forming a stacked gate structure over the first conductive type substrate, wherein the stacked gate structure comprises a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate sequentially stacked over the first conductive type substrate and the stacked gate structure is disposed over the second conductive type shallow well;
• forming a first conductive type source region and a first conductive type drain region in the first conductive type substrate within the second conductive type shallow well on each side of the stacked gate structure;
• forming a doped region within the first conductive type drain region such that the doped region passes through the junction between the first conductive type drain region and the second conductive type shallow well;
• forming a metal silicide layer within the first conductive type drain region such that the metal silicide layer is electrically connected to the doped region;
• forming an inter-layer dielectric layer over the first conductive type substrate and the stacked gate structure, wherein the inter-layer dielectric layer has an opening that exposes a portion of the first conductive type drain region;
• and
• forming a contact plug inside the opening of the inter-layer dielectric layer such that the contact plug is electrically connected to the metal silicide layer.