Method of isolating memory cells
OwnerChandra Mouliinventor
Life of this patent
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Abstract
The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between adjacent active areas of an integrated circuit structure, for example a DRAM memory cell. An aluminum oxide (Al2O3) is used as a gate dielectric, rather than a conventional gate oxide layer, to create a hole-rich accumulation region under and near the trench isolation region. Another exemplary embodiment of the invention provides an aluminum oxide layer utilized as a liner in a shallow trench isolation (STI) region to increase the effectiveness of the isolation region. The embodiments may also be used together at an isolation region.
Claims14
1-15. (canceled)
A method of isolating active areas of a memory cell array, the method comprising:
- providing a memory cell array, each memory cell of said array comprising at least one active area and an isolation gate comprising a layer of aluminum oxide, said gate adjacent said at least one active area;
- connecting said isolation gate to a terminal for receiving a voltage potential;
- and
- applying the potential to said isolation gate through said terminal.
A method of forming an isolation region between active areas on a memory cell array, said method comprising:
- providing a memory cell array having a plurality of active areas formed on a substrate;
- forming a shallow trench in the substrate between two adjacent active areas of said array;
- and
- lining said trench with an aluminum oxide layer.
28-57. (canceled)
Dependencies are inferred from the claim text.