SRAM devices having buried layer patterns and methods of forming the same

A static random access memory (SRAM) device, comprising:

• a semiconductor substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region;
• a plurality of cell gate patterns sequentially stacked on the active region in the cell array region;
• a plurality of peripheral gate patterns formed on the active regions in the peripheral circuit region;
• metal silicide layers disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the at least one portion of the peripheral gate patterns, respectively;
• etching protective layer patterns and buried layer patterns disposed on the at least one portion of the peripheral gate patterns and at least partially on the metal silicide layers and the semiconductor substrate;
• and
• an etch stop layer and a protective interlayer-insulating layer disposed on the cell array region and on regions around the at least one portion of the peripheral gate patterns,
• wherein the protective interlayer-insulating layer and the etch stop layer surround the buried layer patterns and the etching protective layer patterns, and the etching protective layer patterns are disposed between the buried layer patterns and the protective interlayer-insulating layer and extend away from a top surface of the semiconductor substrate.

A method of forming a static random access memory (SRAM) device, comprising:

• providing a semiconductor substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region;
• forming cell gate patterns sequentially stacked on at least one cell active region in the cell array region and peripheral gate patterns on the peripheral active regions in the peripheral circuit region,
• forming an etch stop layer on the peripheral gate patterns and a portion of the cell gate patterns;
• forming a protective interlayer-insulating layer on the etch stop layer, the protective interlayer-insulating layer isolating the cell gate patterns from each other;
• exposing at least one portion of the peripheral gate patterns and the semiconductor substrate near the at least one portion of the peripheral gate patterns;
• forming metal silicide layers on the at least one portion of the peripheral gate patterns and on the semiconductor substrate near the at least one portion of the peripheral gate patterns, respectively;
• and
• forming buried layer patterns on the metal silicide layers.

A method of forming a static random access memory (SRAM) device, comprising:

• providing a semiconductor substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region;
• forming sequentially stacked cell gate patterns on the active region in the cell array region and peripheral gate patterns on the active regions in the peripheral circuit region;
• forming an etch stop layer on the peripheral gate patterns and portions of cell gate patterns;
• forming a protective interlayer-insulating layer on the etch stop layer and isolating the cell gate patterns from each other;
• exposing at least one portion of the peripheral gate patterns and the semiconductor substrate near the at least one portion of the peripheral gate patterns in the peripheral circuit region;
• forming metal silicide layers on the at least one portion of the peripheral gate patterns and on the semiconductor substrate near the at least one portion of the peripheral gate patterns;
• and
• forming etching protective layer patterns and buried layer patterns on the metal silicide layers.