Chip-scale package for integrated circuits

A composite wafer, comprising:

• a plurality of singulated die chips, each of the plurality of die chips comprising at least one die and at least one electrical contact point associated with the at least one die;
• at least a portion of a first cap wafer defining a plurality of passages therethrough, each of the plurality of passages being at a respective position corresponding to a location of a respective one of the at least one electrical contact point on one of the plurality of singulated die chips;
• and
• electrically conductive material filling each passage and extending from a first surface of the at least a portion of the first cap wafer to a second surface thereof, and
• for each passage, an electrical connection between the end of the electrically conductive material at the first surface of the at least a portion of the first cap wafer and the respective electrical contact point on the one of the plurality of singulated die chips.

A multi-story, chip-scale packaged integrated circuit, comprising:

• a carrier comprising first and second mounting surfaces and a third surface;
• a plurality of package contact pads on the third surface of the carrier;
• a first die chip bonded to at least a portion of the first mounting surface and electrically connected to at least one of the plurality of package contact pads;
• and
• a second die chip bonded to at least a portion of the second mounting surface and electrically connected to at least one of the plurality of package contact pads.

A multi-story, chip-scale packaged integrated circuit, comprising:

• a carrier comprising first and second mounting surfaces and a third surface;
• a plurality of package contact pads on the third surface of the carrier;
• a first die chip bonded to the first mounting surface and electrically connected to at least one of the plurality of package contact pads;
• and
• a second die chip bonded to the second mounting surface and electrically connected to the first die chip.