ESD protection circuit with low parasitic capacitance

An integrated circuit (IC) layout for an electrostatic discharge (ESD) protection circuit having a silicon controlled rectifier (SCR) for bypassing an ESD current from a core circuitry during an ESD event, and a MOS transistor for reducing a trigger voltage of the silicon controlled rectifier during the ESD event, the IC layout comprising:

• an SCR diode area for placement of a first diode and a second diode, which are serially connected with one another in an opposite direction, for serving as a bipolar transistor that, in part, constructs the SCR;
• and
• at least two sets of MOS transistor areas, having a plurality of transistors jointly functioning as the MOS transistor, disposed proximately at two sides of the SCR diode area,
• wherein the MOS transistor areas have substantially identical width ranging from 2 to 480 μm,
• wherein a parasitic capacitance of the ESD protection circuit is adjusted by varying a number or size of the MOS transistor areas.