Isolation cell used as an interface from a circuit portion operable in a power-down mode to a circuit portion in a power-up mode

An isolation cell provided between an output of a first module and an input of a second module, said first module being operable in a power-down mode or a power-up mode while said second module is operable in said power-up mode, said isolation cell comprising:

• a first push-pull inverter containing a first transistor and a second transistor, the gate terminal of each of said first transistor connected to said output of said first module;
• a second push-pull inverter containing a third transistor and a fourth transistor, the gate terminal of each of said third transistor and said fourth transistor being connected to the output of said first push-pull inverter, the output of said second push-pull inverter connected to said input of said second module;
• a fifth transistor having a source terminal connected to a power supply and a drain terminal connected to provide power to said first push-pull inverter and said second push-pull inverter;
• a sixth transistor having a drain terminal connected to said input of said second module and a source terminal connected to ground,
• a gate terminal of each of said fifth transistor and sixth transistor connected to a status signal indicating whether said first module is in said power-down mode or said power-up mode,
• one of said fifth transistor and said sixth transistor comprising a PMOS transistor and the other one of said fifth transistor and said sixth transistor comprising a NMOS transistor.