Method for improving accuracy of MOSFET models used in circuit simulation integrated circuits

A method for improving accuracy of MOSFET models used in circuit simulation of integrated circuits, said method comprising:

• a) receiving the original design, corresponding netlists used in circuit simulation, compact transistor models required by the said netlists and polygonal description of as manufactured patterns of the original design elements
• b) partitioning the geometric elements of as-manufactured patterns corresponding to MOSFET devices in which cutlines are placed across the nonrectangular transistor gates in the source-drain direction to divide transistors into narrower slices. Measuring linear dimensions of these transistor slices.
• c) indexing of the transistor slices which calculates and assigns width (W), length (L), and distance from edge (Z) parameters to each transistor slice
• d) replacing each transistor in the original netlist with a sub-circuit consisting of one or more transistors corresponding to the transistor slices created by partitioning “b”
• e) generating a new set of model parameters for each transistor in the subcircuit created in “d”, using the original transistor models received in “a” and values of L and W parameters calculated in “c”