Method of forming semiconductor device having epitaxial contact plug connecting stacked transistors

A method of manufacturing a semiconductor device, the method comprising:

• forming an insulating interlayer on a semiconductor substrate;
• forming an opening in the insulating interlayer to expose source/drain regions of a transistor formed in the semiconductor substrate;
• forming a mushroom-shaped epitaxial plug on the source/drain regions using a selective epitaxial growth (SEG) process;
• forming a buffer layer on the insulating interlayer and the epitaxial plug;
• and,
• planarizing the buffer layer and the epitaxial plug using a chemical mechanical polishing (CMP) process to expose a top surface of the insulating interlayer, thereby forming an epitaxial contact plug.

A method of manufacturing a semiconductor device, the method comprising:

• forming an insulating interlayer on a semiconductor substrate;
• forming an opening in the insulating interlayer to expose first source/drain regions in a lower transistor formed in the semiconductor substrate;
• forming a mushroom-shaped epitaxial plug on the first source/drain regions using a selective epitaxial growth (SEG) process;
• forming a buffer layer on the insulating interlayer and the epitaxial plug;
• planarizing the buffer layer and the epitaxial plug using a chemical mechanical polishing (CMP) process to expose a top surface of the insulating interlayer, wherein the planarized epitaxial plug forms an epitaxial contact plug;
• forming a semiconductor pattern on the epitaxial contact plug in contact with the epitaxial contact plug;
• and, forming an upper transistor on the semiconductor pattern.