Method of manufacturing semiconductor integrated circuit

A method of manufacturing a semiconductor integrated circuit comprising a logic part and a memory array part, said logic part comprised of an N channel type field effect transistor and a P channel type field effect transistor, and said memory array part comprised of an N channel type field effect transistor and a P channel type field effect transistor, said method comprising the steps of:

• (A) forming gate parts, channel forming regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said logic part, and gate parts, channel forming regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said memory array part, in a semiconductor substrate;
• (B) forming a first insulation film having a tensile stress on the whole surface and forming a second insulation film on said first insulation film;
• (C) selectively removing said second insulation film and said first insulation film present on the upper side of the region of said P channel type field effect transistor constituting said logic part;
• (D) forming a third insulation film having a compressive stress on the whole surface;
• and
• (E) applying ion implantation for relaxation of compressive stress to said third insulation film present on the upper side of the region of said N channel field effect transistor constituting said memory array part, and selectively removing said third insulation film present on the upper side of the region of said N channel type field effect transistor constituting said logic part.

A method of manufacturing a semiconductor integrated circuit comprising a logic part and a memory array part, said logic part comprised of an N channel type field effect transistor and a P channel type field effect transistor, and said memory array part comprised of an N channel type field effect transistor and a P channel type field effect transistor, said method comprising the steps of:

• (A) forming gate parts, channel forming regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said logic part, and gate parts, channel forming regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said memory array part, in a semiconductor substrate;
• (B) forming a first insulation film having a tensile stress on the whole surface and forming a second insulation film on said first insulation film;
• (C) selectively removing said second insulation film present on the upper side of said regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said logic part;
• (D) selectively removing said first insulation film present on said region of said P channel type field effect transistor constituting said logic part;
• (E) forming a third insulation film having a compressive stress on the whole surface;
• and
• (F) selectively removing said third insulation film present on the upper side of said region of said N channel type field effect transistor constituting said logic part and said third insulation film present on the upper side of said regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said memory array part.

A method of manufacturing a semiconductor integrated circuit comprising a logic part and a memory array part, said logic part comprised of an N channel type field effect transistor and a P channel type field effect transistor, and said memory array part comprised of an N channel type field effect transistor and a P channel type field effect transistor, said method comprising the steps of:

• (A) forming gate parts, channel forming regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said logic part, and gate parts, channel forming regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said memory array part, in a semiconductor substrate;
• (B) forming a first insulation film having a tensile stress on the whole surface and forming a second insulation film on said first insulation film;
• (C) selectively removing said second insulation film present on the upper side of the regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said logic part;
• (D) selectively removing said first insulation film present on the region of said P channel type field effect transistor constituting said logic part;
• (E) forming a third insulation film having a compressive stress on the whole surface;
• and
• (F) applying ion implantation for relaxation of compressive stress to said third insulation film present on the upper side of the region of said N channel type field effect transistor constituting said memory array part, and selectively removing said third insulation film present on the upper side of the region of said N channel type field effect transistor constituting said logic part.

A method of manufacturing a semiconductor integrated circuit comprising a logic part and a memory array part, said logic part comprised of an N channel type field effect transistor and a P channel type field effect transistor, and said memory array part comprised of an N channel type field effect transistor and a P channel type field effect transistor, said method comprising the following steps:

• (A) forming gate parts, channel forming regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said logic part, and gate parts, channel forming regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said memory array part, in a semiconductor substrate;
• (B) forming a first insulation film having a tensile stress on the whole surface and forming a second insulation film on said first insulation film;
• (C) selectively removing said second insulation film and said first insulation film present on the upper side of the region of said N channel type field effect transistor constituting said logic part;
• (D) forming a third insulation film having a compressive stress on the whole surface;
• and
• (E) selectively removing said third insulation film present on the upper side of the region of said P channel type field effect transistor constituting said logic part, wherein
• between any two of said steps (B) to (D), ion implantation for relaxation of compressive stress is applied to said first insulation film present on the region of said N channel type field effect transistor constituting said memory array part.