Semiconductor device having optimized shallow junction geometries and method for fabrication thereof

A method of manufacturing an integrated circuit, comprising:

• forming metal oxide semiconductor (MOS) transistor devices, including:
• forming a first gate structure over a first dopant region and forming a second gate structure over a second dopant region;
• growing an oxide layer from a substrate over the first and second dopant regions;
• implanting a first dopant through the oxide layer, into the substrate in the first dopant region, and adjacent the first gate structure;
• forming a protective layer over the first dopant region;
• substantially removing the oxide layer from the substrate within the second dopant region with a buffered hydrofluoric acid (BHF) solution wherein a ratio of parts of ammonium fluoride to parts of hydrofluoric acid is at least about 300:1 such that a the protective layer is not substantially damaged or removed;
• and
• implanting a second dopant opposite in type to the first dopant into the substrate within the second dopant region, adjacent a second gate structure, and subsequent to substantially removing the oxide layer;
• and
• interconnecting the MOS transistor devices with interconnects located in dielectric layers overlying the MOS transistor devices.