CMOS silicide metal gate integration

A method of forming a CMOS structure having silicide contacts comprising the step of:

• providing a structure comprising a plurality of polySi gates overlying a semiconductor substrate;
• depositing a silicide metal atop the structure including the polySi gates and the semiconductor substrate;
• forming a recessed, reflow material between each polySi gate;
• removing silicide metal from atop each of the polySi gates;
• removing the recessed, reflow material;
• and
• annealing the structure so as to form silicide contact regions between each of the polySi gates.

A method of forming a CMOS structure having silicide contacts comprising the step of:

• providing a structure comprising a plurality of polySi gates overlying a semiconductor substrate;
• forming a bilayer layer comprising a metal-containing layer and a capping layer atop the structure including the polySi gates and the semiconductor substrate;
• forming a planarizing material on the semiconductor substrate;
• exposing the metal-containing layer atop each polySi gate;
• removing the metal-containing layer from atop each polySi gate;
• planarizing the planarizing material;
• and
• annealing the structure so as to form silicide contact regions between each of the polySi gates.