Charge modulation network for multiple power domains for silicon-on-insulator technology
AssigneeInternational Business Machines Corporation
InventorsDavid Cain, Jeffrey Gambino, Norman Rohrer, Daryl Seitzer, Steven Voldman
Life of this patent
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Abstract
An SOI integrated circuit includes ESD protection on an SOI chip. A first power domain and a second power domain are provided in the SOI chip. In one embodiment , a charge modulation network in the SOI chip between the first power domain and the second power domain mitigates accumulation of electrical charge in an electrically isolated region of the SOI chip. In another embodiment, an ESD protection device in the SOI chip electrically connects the first power domain and the second power domain via a low metal layer to provide a discharge path for accumulated charge.
Claims20
A method of implementing electrostatic discharge (ESD) protection in a silicon-on-insulator (SOI) integrated circuit comprising:
- providing a first power domain and a second power domain in the SOI integrated circuit;
- and
- providing a charge modulation network in the SOI integrated circuit between the first power domain and the second power domain to mitigate accumulation of electrical charge in an electrically isolated region of the SOI integrated circuit.
A silicon-on-insulator (SOI) integrated circuit including electrostatic discharge (ESD) protection comprising:
- an SOI chip;
- a first power domain in the SOI chip;
- a second power domain in the SOI chip;
- and
- a charge modulation network in the SOI chip between the first power domain and the second power domain to mitigate accumulation of electrical charge in an electrically isolated region of the SOI chip.
A silicon-on-insulator (SOI) integrated circuit including electrostatic discharge (ESD) protection comprising:
- an SOI chip;
- a first power domain in the SOI chip;
- a second power domain in the SOI chip;
- and
- an ESD protection device in the SOI chip electrically connecting the first power domain and the second power domain via a low metal layer to provide a discharge path for accumulated charge.
A method of implementing electrostatic discharge protection in a silicon-on-insulator (SOI) integrated circuit comprising:
- defining a plurality of SOI devices in the integrated circuit;
- identifying a plurality of power domains in the SOI integrated circuit;
- determining if a logic signal traverses more than one of the plurality of power domains;
- determining if a circuit path for the logic signal is timing critical;
- and
- connecting a power supply wire for an ESD protection network at a metal level lower than or equal to a highest metal level on which the logic signal is routed if the logic signal traverses more than one power domain and if the circuit path is timing critical.
Dependencies are inferred from the claim text.