Charge-trapping memory device and method for production
AssigneeInfineon Technologies AG
InventorsHarald Seidl, Josef Willer, Martin Gutsche
Life of this patent
Estimating the term…
Abstract
A thin SiGe layer is provided as an additional lower gate electrode layer and is arranged between a thin gate oxide and a gate electrode layer, preferably of polysilicon. The SiGe layer can be etched selectively to the gate electrode and the gate oxide and is laterally removed adjacent the source/drain regions in order to form recesses, which are subsequently filled with a material that is appropriate for charge-trapping. The device structure and production method are appropriate for an integration scheme comprising local interconnects of memory cells, a CMOS logic periphery and means to compensate differences of the layer levels in the array and the periphery.
Claims21
A method for fabricating semiconductor memory devices, the method comprising:
- forming a gate oxide on a surface of a semiconductor body;
- depositing an SiGe layer on said gate oxide;
- depositing a gate electrode layer and a wordline layer on said SiGe layer;
- structuring said wordline layer, said gate electrode layer, and said SiGe layer to form wordline stacks;
- etching residual parts of said SiGe layer selectively to said gate oxide and said gate electrode layer to form underetched recesses beneath said gate electrode layer within said SiGe layer on both sides of said wordline stacks;
- forming an oxide layer on surfaces of the semiconductor body, of remaining parts of said SiGe layer, and of said gate electrode layer;
- depositing a material that is provided for a memory layer;
- and
- removing said material except for residual parts that form striplike memory layers beneath lower edges of said gate electrode layer.
A method of fabricating a semiconductor memory device, the method comprising:
- forming a plurality of wordline stacks over a semiconductor body, each wordline stack including an SiGe layer, a conductive material overlying the SiGe layer and a hardmask overlying the conductive material;
- forming an undercut region beneath the wordline stack by selectively etching the SiGe layer relative to the conductive material;
- applying a memory layer sequence between the wordline stacks in the undercut region;
- forming source/drain regions in the semiconductor body between the wordline stacks;
- forming a gap filling between the wordline stacks to an upper surface level of the hardmask;
- applying a cap layer over the gap filling and the hardmask;
- removing the cap layer and an upper portion of the gap filling in an area provided for contact holes thereby forming recesses within the gap filling;
- forming spacers on sidewalls of the recesses;
- further removing the gap filling to form contact holes, thereby leaving gap filling residues on sidewalls of the wordline stacks beneath the spacers;
- and
- forming an electrically conductive material within the contact holes.
15-19. (canceled)
A method of fabricating a semiconductor memory device, the method comprising:
- providing a semiconductor body;
- forming a gate insulating layer over the semiconductor body;
- forming an SiGe layer over the gate insulating layer;
- forming a gate electrode layer over the SiGe layer, the gate electrode layer and the SiGe layer forming a gate electrode that is arranged above a channel region and separated from the channel region by the gate insulating layer;
- laterally recessing the SiGe layer under the gate electrode layer;
- forming source/drain regions at a main surface of the semiconductor body adjacent sidewalls of the gate electrode;
- and
- forming memory layers of material that is suitable for charge-trapping between the gate electrode layer and the source/drain regions on both sides of the SiGe layer.
Dependencies are inferred from the claim text.