Method for optimising transistor performance in integrated circuits
AssigneeIcera Inc.
InventorsPeter Hughes, Shannon Morton, Trevor Monk
Life of this patent
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Abstract
A method (300) for optimising transistor performance in semiconductor integrated circuits built from standard cells (12), or custom transistor level layout, is disclosed. An active area of NMOS diffusion is extended with a joining area (102) between two adjacent cells (112) having the same net on diffusion at the adjacent edges of each cell. The diffusion area is extended to limit the occurrence of active and nonactive interface to minimise lattice strain effects and improve transistor performance.
Claims38
A method for optimising transistor performance in an integrated circuit, comprising:
- providing an integrated circuit having at least two cells, each cell having a logic function defined by the interconnection between active regions, non-active regions and power rails, each cell having an edge defined by a non-active regions each cell having a connection between an active diffusion region and a power rail;
- identifying at least two adjacent cells each having a corresponding connection between an active region to the same power rail;
- and
- joining the respective active regions associated with each corresponding connection of each cell with an additional diffusion area across the boundary between the cells forming the connected diffusion of the two adjacent cells.
A method for building an integrated circuit having a connected diffusion cell architecture, comprising:
- providing a logic cell library having at least one cell, each cell having a logic function defined by the interconnection between active regions, non-active regions and power rails, each cell having an edge defined by a non-active region, each cell having a connection between an active region and a power rail;
- placing cells from the logic cell library into the integrated circuit;
- identifying at least two adjacent cells in the integrated circuit each having a corresponding connection between an active region to the same power rail;
- and
- joining the respective active regions associated with each corresponding connection of each cell with an additional diffusion area across the boundary between the cells forming the connected diffusion of the two adjacent cells.
An integrated circuit having a connected diffusion cell architecture, comprising:
- at least two adjacent cells, each cell having a logic function defined by the interconnection between active regions, non-active regions and power rails, each cell having an edge defined by a non-active region, each cell having a connection between an active region and a power rail;
- additional diffusion area across the boundary between the cells joining the respective active diffusion region associated with the corresponding connection of each cell forming the connected diffusion of the two adjacent cells.
Dependencies are inferred from the claim text.