Semiconductor apparatus and complimentary MIS logic circuit

A semiconductor apparatus forming an insulating isolation region on a silicon substrate of an SOI structure, wherein:

• the semiconductor apparatus comprises:
• a perfectly depleted or close to being perfectly depleted partially depleted-type N-channel MIS transistor, formed on an electrically insulated silicon substrate surrounded by the insulating isolation region;
• and
• an N-channel MIS transistor for substrate potential control use, provided between a source electrode of the N-channel MIS transistor and the silicon substrate;
• a gate electrode of the N-channel MIS transistor and a gate electrode of the N-channel MIS transistor for substrate potential control use are connected;
• and
• silicon substrate potential becomes the same as the source potential when the N-channel MIS transistor goes on.

A semiconductor apparatus forming an insulating isolation region on a silicon substrate of an SOI structure, wherein:

• the semiconductor apparatus comprises:
• a perfectly depleted or close to being perfectly depleted partially depleted-type P-channel MIS transistor, formed on an electrically insulated silicon substrate surrounded by the insulating isolation region;
• and
• a P-channel MIS transistor for substrate potential control use, provided between a source electrode of the P-channel MIS transistor and the silicon substrate;
• a gate electrode of the P-channel MIS transistor and a gate electrode of the P-channel MIS transistor for substrate potential control use are connected;
• and
• silicon substrate potential becomes the same as the source potential when the P-channel MIS transistor goes on.

A semiconductor apparatus forming an insulating isolation region on an SOI structure silicon substrate, wherein:

• the semiconductor apparatus comprises:
• one or a plurality of perfectly depleted or close to being perfectly depleted partially depleted-type N-channel MIS transistors formed on an electrically insulated silicon substrate surrounded by the insulating isolation region;
• a capacitor formed using an insulating film;
• and
• an N-channel MIS transistor for substrate potential control use;
• the N-channel MIS transistor for substrate potential control use is connected between source electrodes of the one or a plurality of N-channel MIS transistors and the silicon substrate;
• an electrode connected to a gate electrode of the N-channel MIS transistor for substrate potential control use and an impurity diffusion layer formed within the silicon substrate and diffused with the same impurities as the silicon substrate are connected via the capacitor;
• and
• the capacitor and the gate electrode of the N-channel MIS transistor for substrate potential control use are isolated from the one or plurality of N-channel MIS transistor gate electrodes.

A semiconductor apparatus forming an insulating isolation region on a silicon substrate of an SOI structure, wherein:

• the semiconductor apparatus comprises:
• one or a plurality of perfectly depleted or close to being perfectly depleted partially depleted-type P-channel MIS transistors formed on an electrically insulated silicon substrate surrounded by the insulating isolation region;
• a capacitor formed using an insulating film;
• and
• a P-channel MIS transistor for substrate potential control use;
• the P-channel MIS transistor for substrate potential control use is connected between source electrodes of the one or a plurality of P-channel MIS transistors and the silicon substrate;
• an electrode connected to a gate electrode of the P-channel MIS transistor for substrate potential control use and an impurity diffusion layer formed within the silicon substrate and diffused with the same impurities as the silicon substrate are connected via the capacitor;
• and
• the capacitor and the gate electrode of the P-channel MIS transistor for substrate potential control use are isolated from the one or plurality of P-channel MIS transistor gate electrodes.