Intercommunicating apparatus for duplex system capable of detecting failure thereof
AssigneeNEC Corporation
InventorHirofumi Sudo
Life of this patent
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AssigneeNEC Corporation
InventorHirofumi Sudo
Estimating the term…
A parity generating circuit in a 0 side receives input signals on respective signal lines and produces a parity bit based on the input signals. A parallel/serial converting circuit multiplexes parallel signals (or input signals) and the parity bit into a serial signal with reference to a timing signal. A serial/parallel converting circuit in a 1 side reproduces parallel signals and a parity signal and produces a parity check timing signal. A parity checking circuit checks a parity of the parallel signals by the use of the parity signal. If normal, a state holding circuit holds outputs of the parity checking circuit as a state signal. If abnormal, held content of the state holding circuit is cleared.
A method for transmitting a plurality of intercommunicating signals parallel to one another from a first processor unit to a second processor unit of a duplex processor apparatus, said method comprising the steps of:
A method for transmitting a plurality of intercommunicating signals parallel to one another from a first processor unit to a second processor unit of a duplex processor apparatus, said method comprising the steps of:
Dependencies are inferred from the claim text.