Test system

A test system comprising:

• a test target system operating according to a system clock;
• a test bus implemented using part or all of an input/output bus which is originally designed to transfer input and output data to and from the test target system;
• a plurality of input circuits, each said input circuit including an associated input port, a first input register connected to the test bus and a first shift register operating according to a shift clock independent of the system clock, so as to supply first data input from said associated input port to the test target system via the test bus;
• and
• a plurality of output circuits, each said output circuit including an associated output port, a second input register connected to the test bus and a second shift register operating according to the shift clock, so as to supply second data, which has been supplied from the test target system to the test bus, to said associated output port,
• the plurality of first shift registers and the plurality of second shift registers being connected in series to form a scan path chain,
• wherein, when the test target system is tested, initial state setting is performed by setting input and output data on the test bus to the first and second input registers, and, after the system clock is activated, the first data of the input circuits is loaded into the first shift registers or the second data of the output circuits is loaded into the second shift registers, and the shift clock is activated to extract the first data of the input circuits or the second data of the output circuits from the scan path chain.

A test system comprising:

• a test target system operating according to a system clock;
• a test bus implemented using part or all of an input/output bus which is originally designed to transfer input and output data to and from the test target system;
• a plurality of input circuits, each said input circuit including an associated input port, a first input register connected to the test bus and a first shift register operating according to a shift clock independent of the system clock, so as to supply first data input from said associated input port to the test target system via the test bus;
• and
• a plurality of output circuits, each said output circuit including an associated output port, a second input register connected to the test bus and a second shift register operating according to the shift clock, so as to supply second data, which has been output from the test target system to the test bus, to said associated output port,
• the plurality of first shift registers and the plurality of second shift registers being connected in series to form a scan path chain,
• wherein, when the test target system is tested, initial state setting is performed by setting input and output data on the test bus to the first and second input registers, and, after the system clock is activated, the first data of the input circuits or the second data of the output circuits is output to the test bus.

A test system comprising:

• a test target system operating according to a system clock;
• a test bus implemented using part or all of an input/output bus for transferring input and output data in the test target system;
• a plurality of input circuits, each said input circuit including an associated input port, a first input register connected to the test bus and a first shift register operating according to a shift clock independent of the system clock, so as to supply first data input from said associated input port to the test target system via the test bus;
• and
• a plurality of output circuits, each said output circuit including an associated output port, a second input register connected to the test bus and a second shift register operating according to the shift clock, so as to supply second data, which has been given from the test target system to the test bus, to said associated output port,
• the plurality of first shift registers and the plurality of second shift registers being connected in series to form a scan path chain,
• wherein, when the test target system is tested, initial state setting is performed by setting input and output data on the test bus to the first and second input registers, and, after the system clock is activated, enable data is circulated in the scan path chain, and the first data of the input circuits and the second data of the output circuits are sent to the test bus if values of the first and second shift registers are active whereas the first data of the input circuits and the second data of the output circuits are not sent to the test bus if values of the first and second shift registers are inactive.