Method and apparatus for testing an electronic device

A device comprising:

• a scan controller configured to be coupled to an integrated circuit and configured to perform a connectivity test on the integrated circuit by transmitting a command signal to the integrated circuit, wherein the command signal:
• places the integrated circuit into a test mode;
• causes a register assembly located on the integrated circuit to drive a test signal onto a conductive interconnect;
• and
• places the register assembly into a neutral state, wherein the integrated circuit is placed in a neutral state without the integrated circuit exiting the test mode.

A method of testing an electronic device comprising:

• performing a first connectivity test on a trace in accordance with IEEE 1149.1, wherein the trace is disposed between two integrated circuits;
• placing the trace into a neutral state, wherein the placing the trace into a neutral state does not involve the two integrated circuits exiting external boundary test mode;
• and
• performing a second connectivity test on the trace in accordance with IEEE 1149.1.

A method of performing a connectivity test comprising:

• entering a test mode;
• loading a first test pattern into a first integrated circuit;
• driving a first test signal from the first integrated circuit to a second integrated circuit;
• and
• placing the first integrated circuit and the second integrated circuit in a neutral state.

A system for performing a connectivity test comprising:

• a first integrated circuit configured to operate in a test mode;
• a second integrated circuit coupled to the first integrated circuit by a conductive interconnect and configured to operate in the test mode;
• and
• a scan controller configured to perform two connectivity tests involving the conductive interconnect, wherein the first integrated circuit is configured to place the conductive interconnect in a neutral state between the two connectivity tests without either the first integrated circuit or the second integrated circuit exiting the test mode.

A tangible medium storing instructions to be run on a computer, the instructions comprising:

• code adapted to place a first integrated circuit into a test mode, wherein the first integrated circuit is coupled to a conductive interconnect;
• code adapted to cause a register assembly located on the first integrated circuit to transmit a test signal onto the conductive interconnect;
• and
• code adapted to place the register assembly into a neutral state, wherein the first integrated circuit is placed into the neutral state without the first integrated circuit exiting test mode.

A system for performing a connectivity test comprising:

• means for entering a test mode;
• means for loading a first test pattern into a first integrated circuit;
• means for driving a first test signal from the first integrated circuit to a second integrated circuit;
• and
• means for placing the first integrated circuit and the second integrated circuit in a neutral state.