Fault detecting method and layout method for semiconductor integrated circuit

A fault detecting method for a semiconductor integrated circuit comprising:

• providing a fault list comprising information identifying physical sites on a physical layout of a semiconductor integrated circuit where a possible fault is likely to occur, and information related to reducing faults;
• detecting faults in accordance with the fault list in a semiconductor integrated circuit to which said fault list corresponds;
• weighting possible faults at physical sites according to their likelihood to achieve a specific fault coverage, thereby creating weighted possible faults;
• and
• providing fault coverage by identifying a fault coverage value from the sum of the weighted fault coverage of detected weighted possible faults,
• wherein said fault list is a weighted fault list with respect to all faults listed therein, and said fault coverage is a rate of fault coverage detected by the weighted fault list.