Memory technology test apparatus
OwnerJoseph Jeddelohinventor
Life of this patent
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Abstract
A programmable control device that creates an environment for controlling, testing and evaluating memory designs. The control device provides automated testing of address eyes, data eyes and voltage margins. The control device interfaces with a conventional computer system, such as a personal computer (PC). The computer system gathers test data and outputs the data in a graphical format if desired. Since the control device is quickly re-programmable, new memory sequencing, control, timing and power techniques are rapidly proto-typed in an inexpensive and timely manner.
Claims29
1-40. (canceled)
An automated method of testing a memory device comprising the steps of:
- controlling the memory device such that the memory device performs one of a plurality of tests;
- inputting test result data from the memory device;
- evaluating characteristics of the memory device from the test result data;
- and
- modifying the characteristics of the memory device and the manner in which the memory device is controlled based on the evaluation.
A method of testing a memory device comprising the steps of:
- generating requests used to test the memory device;
- testing the memory device based on the generated requests;
- inputting test result data from the memory device;
- evaluating characteristics of the memory device from the test result data;
- and
- modifying at least one of the characteristics of the memory device or the manner in which the memory device is controlled based on the evaluation.
Dependencies are inferred from the claim text.